EVL-4 TPI timestamps drifting badly

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rct
Posts: 47
Joined: Mon Dec 21, 2015 6:24 pm

EVL-4 TPI timestamps drifting badly

Post by rct »

I've turned on the EVL TPI timestamps, and enabled time broadcasts from the panel. I noticed that the EVL's TPI timestamps are drifting badly. Typically the minute is right but the seconds vary considerably. There appears to be a periodic correction every 2-3 hours. The drift seems to be a little over a second every 4 minutes.

Is this a bug in the firmware, or does my board have an oscillator that is out of spec?

Here are some log messages showing the time on a linux box running NTP, the raw TPI message which contains the EVL's timestamp and the panel's time broadcasts. The DSC panel sends a time broadcast every 4 minutes at 0, 4, 8, 12, ..., In the logs below, the time broadcasts from the panel occur pretty typically about 20 seconds after the minute, with a typical variation of around 2 seconds. Note the variation in the TPI timestamp seconds. Also note, when the EVL corrects itself, it's clock shows an offset from the server's clock.

Code: Select all

Jul 07 07:00:21 - DEBUG - core/envisalink.py:handle_line@107: RX RAW < "07:00:00 550070007071696"
Jul 07 07:04:21 - DEBUG - core/envisalink.py:handle_line@107: RX RAW < "07:04:58 55007040707169A"
Jul 07 07:08:21 - DEBUG - core/envisalink.py:handle_line@107: RX RAW < "07:08:57 55007080707169E"
Jul 07 07:12:19 - DEBUG - core/envisalink.py:handle_line@107: RX RAW < "07:12:56 550071207071699"
Jul 07 07:16:21 - DEBUG - core/envisalink.py:handle_line@107: RX RAW < "07:16:54 55007160707169D"
Jul 07 07:20:21 - DEBUG - core/envisalink.py:handle_line@107: RX RAW < "07:20:53 550072007071698"
Jul 07 07:24:21 - DEBUG - core/envisalink.py:handle_line@107: RX RAW < "07:24:51 55007240707169C"
Jul 07 07:28:21 - DEBUG - core/envisalink.py:handle_line@107: RX RAW < "07:28:50 5500728070716A0"
Jul 07 07:32:19 - DEBUG - core/envisalink.py:handle_line@107: RX RAW < "07:32:48 55007320707169B"
Jul 07 07:36:21 - DEBUG - core/envisalink.py:handle_line@107: RX RAW < "07:36:47 55007360707169F"
Jul 07 07:40:21 - DEBUG - core/envisalink.py:handle_line@107: RX RAW < "07:40:45 55007400707169A"
Jul 07 07:44:19 - DEBUG - core/envisalink.py:handle_line@107: RX RAW < "07:44:44 55007440707169E"
Jul 07 07:48:21 - DEBUG - core/envisalink.py:handle_line@107: RX RAW < "07:48:42 5500748070716A2"
Jul 07 07:52:19 - DEBUG - core/envisalink.py:handle_line@107: RX RAW < "07:52:40 55007520707169D"
Jul 07 07:56:21 - DEBUG - core/envisalink.py:handle_line@107: RX RAW < "07:56:39 5500756070716A1"
Jul 07 08:00:21 - DEBUG - core/envisalink.py:handle_line@107: RX RAW < "08:00:37 550080007071697"
Jul 07 08:04:21 - DEBUG - core/envisalink.py:handle_line@107: RX RAW < "08:04:36 55008040707169B"
Jul 07 08:08:19 - DEBUG - core/envisalink.py:handle_line@107: RX RAW < "08:08:35 55008080707169F"
Jul 07 08:12:21 - DEBUG - core/envisalink.py:handle_line@107: RX RAW < "08:12:33 55008120707169A"
Jul 07 08:16:21 - DEBUG - core/envisalink.py:handle_line@107: RX RAW < "08:16:32 55008160707169E"
Jul 07 08:20:21 - DEBUG - core/envisalink.py:handle_line@107: RX RAW < "08:20:30 550082007071699"
Jul 07 08:24:21 - DEBUG - core/envisalink.py:handle_line@107: RX RAW < "08:24:29 55008240707169D"
Jul 07 08:28:19 - DEBUG - core/envisalink.py:handle_line@107: RX RAW < "08:28:27 5500828070716A1"
Jul 07 08:32:21 - DEBUG - core/envisalink.py:handle_line@107: RX RAW < "08:32:26 55008320707169C"
Jul 07 08:36:21 - DEBUG - core/envisalink.py:handle_line@107: RX RAW < "08:36:24 5500836070716A0"
Jul 07 08:40:21 - DEBUG - core/envisalink.py:handle_line@107: RX RAW < "08:40:23 55008400707169B"
Jul 07 08:44:21 - DEBUG - core/envisalink.py:handle_line@107: RX RAW < "08:44:21 55008440707169F"
Jul 07 08:48:19 - DEBUG - core/envisalink.py:handle_line@107: RX RAW < "08:48:20 5500848070716A3"
Jul 07 08:52:21 - DEBUG - core/envisalink.py:handle_line@107: RX RAW < "08:52:18 55008520707169E"
Jul 07 08:56:21 - DEBUG - core/envisalink.py:handle_line@107: RX RAW < "08:56:17 5500856070716A2"
Jul 07 09:00:21 - DEBUG - core/envisalink.py:handle_line@107: RX RAW < "09:00:16 550090007071698"
Jul 07 09:04:21 - DEBUG - core/envisalink.py:handle_line@107: RX RAW < "09:04:14 55009040707169C"
Jul 07 09:08:21 - DEBUG - core/envisalink.py:handle_line@107: RX RAW < "09:08:13 5500908070716A0"
Jul 07 09:12:21 - DEBUG - core/envisalink.py:handle_line@107: RX RAW < "09:12:11 55009120707169B"
Jul 07 09:16:21 - DEBUG - core/envisalink.py:handle_line@107: RX RAW < "09:16:10 55009160707169F"
Jul 07 09:20:21 - DEBUG - core/envisalink.py:handle_line@107: RX RAW < "09:20:09 55009200707169A"
Jul 07 09:24:19 - DEBUG - core/envisalink.py:handle_line@107: RX RAW < "09:24:07 55009240707169E"
Jul 07 09:28:21 - DEBUG - core/envisalink.py:handle_line@107: RX RAW < "09:28:06 5500928070716A2"
Jul 07 09:32:21 - DEBUG - core/envisalink.py:handle_line@107: RX RAW < "09:32:04 55009320707169D"
Jul 07 09:36:21 - DEBUG - core/envisalink.py:handle_line@107: RX RAW < "09:36:03 5500936070716A1"
Jul 07 09:40:21 - DEBUG - core/envisalink.py:handle_line@107: RX RAW < "09:40:01 55009400707169C"
Jul 07 09:44:19 - DEBUG - core/envisalink.py:handle_line@107: RX RAW < "09:44:00 5500944070716A0"
Jul 07 09:48:21 - DEBUG - core/envisalink.py:handle_line@107: RX RAW < "09:48:58 5500948070716A4"
Jul 07 09:52:21 - DEBUG - core/envisalink.py:handle_line@107: RX RAW < "09:52:57 55009520707169F"
Jul 07 09:56:21 - DEBUG - core/envisalink.py:handle_line@107: RX RAW < "09:56:55 5500956070716A3"
Jul 07 10:00:21 - DEBUG - core/envisalink.py:handle_line@107: RX RAW < "10:00:54 550100007071690"
Jul 07 10:04:19 - DEBUG - core/envisalink.py:handle_line@107: RX RAW < "10:04:52 550100407071694"
Jul 07 10:08:21 - DEBUG - core/envisalink.py:handle_line@107: RX RAW < "10:08:51 550100807071698"
Jul 07 10:12:21 - DEBUG - core/envisalink.py:handle_line@107: RX RAW < "10:12:49 550101207071693"
Jul 07 10:16:21 - DEBUG - core/envisalink.py:handle_line@107: RX RAW < "10:16:48 550101607071697"
Jul 07 10:20:21 - DEBUG - core/envisalink.py:handle_line@107: RX RAW < "10:20:46 550102007071692"
Jul 07 10:24:21 - DEBUG - core/envisalink.py:handle_line@107: RX RAW < "10:24:45 550102407071696"
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K-Man
Posts: 141
Joined: Fri Jun 01, 2012 1:08 pm

Re: EVL-4 TPI timestamps drifting badly

Post by K-Man »

As I said on another post, the time on this system is only accurate to the minute so just ignore the seconds portion. It does not come from the panel and the EVL2/3/4 do not have an onboard RTC as the security panel is responsible for that. This is a slave device.
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